Author Name:   karpagam

An overview of semi conductor lay out design Protection

Semi conductor integrated circuit lay out design

Introduction
In the past the components used forerforming electronic function were large and occupied considerable amount of space for instance the size of the first computer was as big as a room. In the era of technological development this reduction of physical spacing is cause by the introduction of the semi conductor chips.

Science behind semi conductor chips
Semi conductor chips is a device that gives effect to programme instructions through circuit fixed on the semi conductor material in a layered form popular examples are RAM,ROM etc traditionally the individual electronic components were connected through wires. In an IC these components are formed from interactions of three different layers like a mutilayered sandwich. The base layer is semi conductor material followed by a material of insulator which is doped in different places so as to form the various electronic components then topped by the conductor material that links electricity through different parts of the circuit.
The first ever legislation to protect the semi conductor is the US namely the semi conductor chip protection act. The act protects the ‘mask work ‘ as defined in 17 USC $ 902. Many countries in their started legislating to protect the semi conductor IC lay out design.

International treaties to govern lay out designs

Effort was also taken on ;the international front by WIPO to lay down standards for protection of IC layout design which came out with a treaty called treaty on Intellectual property with respect to integrated circuit popularity known as the Washington treaty on the integrated circuit.

The treaty defines “integrated circuit” means a product, in its final form or an intermediate form, in which the elements, at least one of which is an active element, and some or all of the interconnections are integrally formed in and/or on a piece of material and which is intended to perform an electronic function, ;“layout-design (topography)” means the three-dimensional disposition, however expressed, of the elements, at least one of which is an active element, and of some or all of the interconnections of an integrated circuit, or such a three-dimensional disposition prepared for an integrated circuit intended for manufacture.

But the treaty failed due to resistance from US and Japan. The next attempt was dome during the drawing up of the TRIPs agreememt. Most of the Washington treaty provisions are in cooperated in TRIPs , the agreement gives exclusive rights to ip holder like importing, selling, or otherwise distributing for commercial purposes a protected layout-design, an integrated circuit in which a protected layout-design is incorporated, or an article incorporating such an integrated circuit only in so far as it continues to contain an unlawfully reproduced layout-design;. The agreement alsorovides certain limitaions like importing, selling, or otherwise distributing for commercial purposes a protected layout-design, an integrated circuit in which a protected layout-design is incorporated, or an article incorporating such an integrated circuit only in so far as it continues to contain an unlawfully reproduced layout-design

Term of protection

When refistrstion is required in certain countries then the term of protection of layoutdesigns shall not end before the expiration of a period of 10 years counted from the date of filing an application for registration or from the first commercial exploitation wherever in the world it occurs.

the term of protection of layout designs shall not end before the expiration of a period of 10 years counted from the date of filing an application for registration or from the first commercial exploitation wherever in the world it occurs. However so the protection lapse in 15 years from the creation of the layout design protection in India in order to comply with TRIPs India's has passed the semi conductor integrated circuit layout design protection Act ;2000 to product Layout designs. According to the Act “semiconductor integrated circuit” means a product having transistors and other circuitry elements which are inseparably formed on a semiconductor material or an insulating material or inside the semiconductor material and designed to perform an electronic circuitry function and “layout-design” means a layout of transistors and other circuitry elements and includes lead wires connecting such elements and expressed in any manner in a semiconductor integrated circuit///

Minimum standard requirements
Layout-designs are prohibited from registration under the Act if they are as follows:
·Not original;
·Have been commercially exploited anywhere in India or in a Convention country i.e. any country that the Government of India notifies in the Official Gazette for the fulfillment of a treaty, convention or an arrangement with any country outside India and which affords to citizens of India similar privileges as are granted to its own citizens;
·Not inherently distinctive;
·Not inherently capable of being distinguishable from any other registered layout-design

Scope of protection
The layout design as such is protected under the Act. If the laayout is incorporated on an IC then layout design along with the IC is protected. If again the IC is applied to any article then the article as a whole is protected.

Filimg of application
It consist of 4 stages namely

Application for registration.—
(1) Any person claiming to be the creator of a layout-design, who is desirous of registering it, shall apply in writing to the Registrar in the prescribed manner for the registration of his layout-design.
(2) Every application under sub-section (1) shall be filed in the office of the Semiconductor Integrated Circuits Layout-Design Registry within whose territorial limits the principal place of business in India of the applicant or in the case of joint application the principal place of business in India of the applicant whose name is first mentioned in the application, as having a place of business in India, is situated.

Advertisement of application—

(1)When an application for registration of a layout-design has been accepted, the Registrar shall, within fourteen days after the date of acceptance, cause the application as accepted to be advertised in the prescribed manner. (2) Where after advertisement of an application— (a) an error in the application has been corrected; or (b) the application has been permitted to be amended under section 12, the Registrar may in his discretion cause the application to be advertised again or, in any case falling under clause (b), may, instead of causing the application to be

(2) advertised again, notify in the prescribed manner the correction or amendment made in the application Opposition to registration.

1) Any person may, within three months from the date of the advertisement or re-advertisement of an application for registration or within such further period, not exceeding one month in the aggregate, as the Registrar, on application made to him in the prescribed manner and on payment of the prescribed fee, allows, give notice in writing in the prescribed manner to the Registrar of opposition to the registration.

(2) The Registrar shall serve a copy of the notice on the applicant for registration and, within two months from the receipt by the applicant of such copy of the notice of opposition, the applicant shall send to the Registrar in the prescribed manner a counter-statement of the grounds on which he relies for his application and if he does not do so, he shall be deemed to have abandoned his application.

(3) If the applicant sends such counter-statement, the Registrar shall serve a copy thereof on the person giving notice of opposition.

(4) Any evidence upon which the opponent and the applicant may rely shall be submitted in the prescribed manner and within the prescribed time to the Registrar, the Registrar shall give an opportunity to them to be heard, if they so desire.

(5) The Registrar shall, after hearing the parties, if so required, and considering the evidence, decide, after taking into account any ground of objection whether relied upon by the opponent or not. (6) When a person giving notice of opposition or an applicant sending a counter-statement after receipt of a copy of such notice neither resides nor carries on business in India, the Registrar may require him to give security for the costs of proceedings before him and, in default of such security being duly given, may treat the opposition or application, as the case may be, as abandoned.

And finally is the registration by the registrar in the register book

Infringement

registered layout-design is infringed by a person who, not being the registered proprietor of the layout-design or a registered user if
(a)does any act of reproducing, whether by incorporating in a semiconductor integrated circuit or otherwise, a registered layout-design in its entirety or any part thereof.

What are not considered infringement

Where a person, on the basis of scientific evaluation or analysis of a registered layout-design, creates another layout-design which is original within the meaning of sub-section (2) of section 7, that person shall have the right to incorporate such another layout-design in a semiconductor integrated circuit or to perform any of the acts referred to in sub-section (1) or sub-section (5) in respect of such another layout-design and such incorporation or performance of any act shall not be regarded as infringement.

Remedy is usually passing off remedy given

Conclusion
Thus the semi conductor integrated circuit design Act 2000 is in compliance with Trips agreement and till now only 2 applications has been filed under the Act. Apart from other IP protection given under other IP laws this Act gives sui generis protection

End-notes
# 17; USC $ 902-914
# Article 2 of Washington treaty
# Article 36 of TRIPs
# Article 37 TRIPs
# Article 38 TRIPs
# ibid
# Semi conductor integrated circuit lay out designs Act 2000 section 2 (r)
# Ibid section 2(h)
# Ibid section 7
# Ibid section 8
# Ibid section 10
# ;Ibid section 11
# Ibid sec 18

 

ISBN No: 978-81-928510-1-3
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